[EMS Discuss] Logic Diagram Challenge

Mr. Clif clif at eugeneweb.com
Wed Jan 15 23:49:07 PST 2014


Ok here is a Quad and gate part that you can do it with just one package:

MC10H104

there may be others.

     Clif

On 01/15/2014 10:40 PM, Mr. Clif wrote:
> Ok ;-)
>
> So when you say that "inverting operations count as NOT gates" do you 
> mean that they aren't counted as gates or that they are "Not 
> operations"  implemented as gates, which of course they are?
>
> One issue with doing this your way in hardware, is that you need three 
> different types of gates unless you are doing it in an FPGA or the like.
>
> Here it is in a shorter logical expression:
> C = A & B; D = !C & A; E = !C & B
>
> I have another way that uses four of the same kind of gate though they 
> may be some what uncommon. ;-)
>
>     Ciao,
>     Clif
>
> On 01/15/2014 10:04 PM, Weston Turner wrote:
>> From a more rigorous or theoretical standpoint, the inverting 
>> operations count as NOT gates. But I guess I didn't say that 
>> inverting equals a NOT. In any case, my four gate solution doesn't 
>> use them. I'll represent it here in Python using four binary bitwise 
>> operators, one AND, one OR, and two XORs.
>>
>> A and B are anded to make C
>> A and B are ored  together into the temp variable t
>> t is xored with B to make D
>> t is xored with A to make E
>>
>> The operations are color coded below. Can this be done with fewer 
>> operations?
>>
>> Python 2.7.3 (default, Nov 11 2012, 18:06:39)
>> >>> *A, B = 0, 0*
>> >>> t = A | B; C = A & B; D = B ^ t; E = A ^ t
>> >>> C, D, E
>> *(0, 0, 0)*
>> >>> *A, B = 0, 1*
>> >>> t = A | B; C = A & B; D = B ^ t; E = A ^ t
>> >>> C, D, E
>> *(0, 0, 1)*
>> >>> *A, B = 1, 0*
>> >>> t = A | B; C = A & B; D = B ^ t; E = A ^ t
>> >>> C, D, E
>> *(0, 1, 0)*
>> >>> *A, B = 1, 1*
>> >>> t = A | B; C = A & B; D = B ^ t; E = A ^ t
>> >>> C, D, E
>> *(1, 0, 0)*
>>
>> Cheers,
>> Weston
>>
>>
>>
>> On Wed, Jan 15, 2014 at 8:42 PM, Mr. Clif <clif at eugeneweb.com 
>> <mailto:clif at eugeneweb.com>> wrote:
>>
>>     Sure I can do it in three but two of the gates have to have one
>>     inverting input each. Since gates often come in quad packs it
>>     might be nice to find a circuit that would use all four in a
>>     pack. Though if it helps my fourth gate is just an inverter and
>>     there are often left over ones from other packages.
>>
>>         Clif
>>
>>
>>
>>
>>
>>     On 01/15/2014 07:42 PM, Weston Turner wrote:
>>
>>         I'm wondering if anyone can implement this logic table with
>>         less than four gates...
>>
>>         A B | C D E
>>         -------------
>>         0 0 | 0 0 0
>>         0 1 | 0 0 1
>>         1 0 | 0 1 0
>>         1 1 | 1 0 0
>>
>>         I figured out a way to implement it with four gates but I'm
>>         wondering if it can be reduced further...
>>
>>         And if you can only figure out a way to do it with four, then
>>         I'm curious to see if you arrived at the same solution I did.
>>
>>         Regards,
>>         Weston
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>>
>>
>
>
>
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