[EMS Discuss] Logic Diagram Challenge

Darrell Perko dperko at efn.org
Thu Jan 16 15:42:43 PST 2014


Yeah, I was thinking in terms of the most basic gates.  Real-world 
solution with lowest component count trumps.

On 1/16/2014 12:41 PM, Mr. Clif wrote:
> So it boils down to how you define gates, are they something you buy 
> or something you draw? ;-)
>
> In my curciut it uses one package with four and / nand gates and I 
> only use three of them. So there is one left over. One of these gates 
> has two outputs which you might say is cheating. However it is a real 
> part with just AND gates in it, and you can build your circuit with 
> that one chip.
>
> Darrell's solution while it doesn't require an inverter, does require 
> two different packages to do it in real life.
>
> So are you implementing this circuit or drawing it? ;-)
>
>     Clif
>
> On 01/16/2014 12:19 PM, Weston Turner wrote:
>> Okay sorry. Clif, you get the prize too I think. But not if you count 
>> an inverter as a gate (but I haven't looked at the IC you specified, 
>> and so I don't know exactly what is involved in producing the 
>> circuit). Care to present a circuit drawing?
>>
>> Regards,
>> Weston
>>
>> On Jan 16, 2014, at 11:59 AM, "Mr. Clif" <clif at eugeneweb.com 
>> <mailto:clif at eugeneweb.com>> wrote:
>>
>>> Um not so fast Weston, my circuit does it with three gates in one 
>>> package with the fourth one left over.
>>>
>>>     Clif
>>>
>>> On 01/16/2014 10:49 AM, Weston Turner wrote:
>>>> Yay! Darrell, you get the prize.
>>>>
>>>> Regards,
>>>> Weston
>>>>
>>>> On Jan 16, 2014, at 3:21 AM, Darrell Perko <dperko at efn.org 
>>>> <mailto:dperko at efn.org>> wrote:
>>>>
>>>>>
>>>>> I think I have a solution using two XOR and one AND, though the 
>>>>> AND is both an output and it feeds back into the input of the 
>>>>> XORs.  That seems like it could cause brief illegal outputs states.
>>>>>
>>>>> On 1/15/2014 11:49 PM, Mr. Clif wrote:
>>>>>> Ok here is a Quad and gate part that you can do it with just one 
>>>>>> package:
>>>>>>
>>>>>> MC10H104
>>>>>>
>>>>>> there may be others.
>>>>>>
>>>>>>     Clif
>>>>>>
>>>>>> On 01/15/2014 10:40 PM, Mr. Clif wrote:
>>>>>>> Ok ;-)
>>>>>>>
>>>>>>> So when you say that "inverting operations count as NOT gates" 
>>>>>>> do you mean that they aren't counted as gates or that they are 
>>>>>>> "Not operations"  implemented as gates, which of course they are?
>>>>>>>
>>>>>>> One issue with doing this your way in hardware, is that you need 
>>>>>>> three different types of gates unless you are doing it in an 
>>>>>>> FPGA or the like.
>>>>>>>
>>>>>>> Here it is in a shorter logical expression:
>>>>>>> C = A & B; D = !C & A; E = !C & B
>>>>>>>
>>>>>>> I have another way that uses four of the same kind of gate 
>>>>>>> though they may be some what uncommon. ;-)
>>>>>>>
>>>>>>>     Ciao,
>>>>>>>     Clif
>>>>>>>
>>>>>>> On 01/15/2014 10:04 PM, Weston Turner wrote:
>>>>>>>> From a more rigorous or theoretical standpoint, the inverting 
>>>>>>>> operations count as NOT gates. But I guess I didn't say that 
>>>>>>>> inverting equals a NOT. In any case, my four gate solution 
>>>>>>>> doesn't use them. I'll represent it here in Python using four 
>>>>>>>> binary bitwise operators, one AND, one OR, and two XORs.
>>>>>>>>
>>>>>>>> A and B are anded to make C
>>>>>>>> A and B are ored  together into the temp variable t
>>>>>>>> t is xored with B to make D
>>>>>>>> t is xored with A to make E
>>>>>>>>
>>>>>>>> The operations are color coded below. Can this be done with 
>>>>>>>> fewer operations?
>>>>>>>>
>>>>>>>> Python 2.7.3 (default, Nov 11 2012, 18:06:39)
>>>>>>>> >>> *A, B = 0, 0*
>>>>>>>> >>> t = A | B; C = A & B; D = B ^ t; E = A ^ t
>>>>>>>> >>> C, D, E
>>>>>>>> *(0, 0, 0)*
>>>>>>>> >>> *A, B = 0, 1*
>>>>>>>> >>> t = A | B; C = A & B; D = B ^ t; E = A ^ t
>>>>>>>> >>> C, D, E
>>>>>>>> *(0, 0, 1)*
>>>>>>>> >>> *A, B = 1, 0*
>>>>>>>> >>> t = A | B; C = A & B; D = B ^ t; E = A ^ t
>>>>>>>> >>> C, D, E
>>>>>>>> *(0, 1, 0)*
>>>>>>>> >>> *A, B = 1, 1*
>>>>>>>> >>> t = A | B; C = A & B; D = B ^ t; E = A ^ t
>>>>>>>> >>> C, D, E
>>>>>>>> *(1, 0, 0)*
>>>>>>>>
>>>>>>>> Cheers,
>>>>>>>> Weston
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> On Wed, Jan 15, 2014 at 8:42 PM, Mr. Clif <clif at eugeneweb.com 
>>>>>>>> <mailto:clif at eugeneweb.com>> wrote:
>>>>>>>>
>>>>>>>>     Sure I can do it in three but two of the gates have to have
>>>>>>>>     one inverting input each. Since gates often come in quad
>>>>>>>>     packs it might be nice to find a circuit that would use all
>>>>>>>>     four in a pack. Though if it helps my fourth gate is just
>>>>>>>>     an inverter and there are often left over ones from other
>>>>>>>>     packages.
>>>>>>>>
>>>>>>>>         Clif
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>>     On 01/15/2014 07:42 PM, Weston Turner wrote:
>>>>>>>>
>>>>>>>>         I'm wondering if anyone can implement this logic table
>>>>>>>>         with less than four gates...
>>>>>>>>
>>>>>>>>         A B | C D E
>>>>>>>>         -------------
>>>>>>>>         0 0 | 0 0 0
>>>>>>>>         0 1 | 0 0 1
>>>>>>>>         1 0 | 0 1 0
>>>>>>>>         1 1 | 1 0 0
>>>>>>>>
>>>>>>>>         I figured out a way to implement it with four gates but
>>>>>>>>         I'm wondering if it can be reduced further...
>>>>>>>>
>>>>>>>>         And if you can only figure out a way to do it with
>>>>>>>>         four, then I'm curious to see if you arrived at the
>>>>>>>>         same solution I did.
>>>>>>>>
>>>>>>>>         Regards,
>>>>>>>>         Weston
>>>>>>>>         _______________________________________________
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>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
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