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    Wow Darrell,<br>
    <br>
    that is elegant, no inverters.. :-)<br>
    <br>
    <div class="moz-cite-prefix">On 01/16/2014 09:39 AM, Darrell Perko
      wrote:<br>
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        Yeah, I suppose it is normal.  That's what the clock is for
        after all.<br>
        <br>
        Attached is my (messy) schematic.  AND on the left, two XOR on
        right.<br>
        <br>
        <img src="cid:part1.04060505.04010600@eugeneweb.com" alt=""><br>
        <br>
        On 1/16/2014 8:58 AM, Mr. Clif wrote:<br>
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        Way to go Darrell!<br>
        <br>
        That sounds perfectly normal except that if I understand you
        correctly you would say that the output of the AND gate
        propagates into the inputs of the XORs.<br>
        <br>
        After I went to bed last night I realized that with the MC10H104
        I can also do it with three of the four gates in just that one
        package. So not only can I do it in three gates I can also do it
        without buying several different gate packages.<br>
        <br>
        Ok Weston you've got two guys that claim to have solved it in
        three gates! :-p what now?<br>
        <br>
            Clif<br>
        <br>
        <div class="moz-cite-prefix">On 01/16/2014 03:21 AM, Darrell
          Perko wrote:<br>
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            I think I have a solution using two XOR and one AND, though
            the AND is both an output and it feeds back into the input
            of the XORs.  That seems like it could cause brief illegal
            outputs states.<br>
            <br>
            On 1/15/2014 11:49 PM, Mr. Clif wrote:<br>
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            Ok here is a Quad and gate part that you can do it with just
            one package:<br>
            <br>
            MC10H104<br>
            <br>
            there may be others.<br>
            <br>
                Clif<br>
            <br>
            <div class="moz-cite-prefix">On 01/15/2014 10:40 PM, Mr.
              Clif wrote:<br>
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              Ok ;-)<br>
              <br>
              So when you say that "<span style="font-family:courier
                new,monospace"><font face="arial,helvetica,sans-serif"><span
                    style="font-family:courier new,monospace"><font
                      face="arial,helvetica,sans-serif">inverting
                      operations count as NOT gates</font></span></font></span>"
              do you mean that they aren't counted as gates or that they
              are "Not operations"  implemented as gates, which of
              course they are?<br>
              <br>
              One issue with doing this your way in hardware, is that
              you need three different types of gates unless you are
              doing it in an FPGA or the like.<br>
              <br>
              Here it is in a shorter logical expression:<br>
              <span style="font-family:courier new,monospace">C = <span
                  style="background-color:rgb(255,242,204)">A & B</span>;
                D = <span style="background-color:rgb(217,234,211)">!C
                  & A</span>; E = <span
                  style="background-color:rgb(207,226,243)">!C & B</span></span><br>
              <br>
              I have another way that uses four of the same kind of gate
              though they may be some what uncommon. ;-)<br>
              <br>
                  Ciao,<br>
                  Clif<br>
              <br>
              <div class="moz-cite-prefix">On 01/15/2014 10:04 PM,
                Weston Turner wrote:<br>
              </div>
              <blockquote
cite="mid:CAF+j1MNa1jkGiqZovWpQXrdEVthOMwn1aiKmuWt=xb7y2rFTmA@mail.gmail.com"
                type="cite">
                <div dir="ltr">
                  <div><span style="font-family:courier new,monospace"><font
                        face="arial,helvetica,sans-serif"><span
                          style="font-family:courier new,monospace"><font
                            face="arial,helvetica,sans-serif">From a
                            more rigorous or theoretical standpoint, the
                            inverting operations count as NOT gates</font></span>.
                        But I guess I didn't say that inverting equals a
                        NOT. In any case, my four gate solution doesn't
                        use them. I'll represent it here in Python using
                        four binary bitwise operators, one AND, one OR,
                        and two XORs. <br>
                        <br>
                        A and B are anded to make C<br>
                        A and B are ored  together into the temp
                        variable t<br>
                        t is xored with B to make D<br>
                        t is xored with A to make E<br>
                        <br>
                      </font></span></div>
                  <div><span style="font-family:courier new,monospace"><font
                        face="arial,helvetica,sans-serif">The operations
                        are color coded below. Can this be done with
                        fewer operations?<br>
                      </font></span></div>
                  <div><span style="font-family:courier new,monospace"><br>
                      Python 2.7.3 (default, Nov 11 2012, 18:06:39) <br>
                      >>> <b>A, B = 0, 0</b><br>
                      >>> t = <span
                        style="background-color:rgb(244,204,204)">A | B</span>;
                      C = <span
                        style="background-color:rgb(255,242,204)">A
                        & B</span>; D = <span
                        style="background-color:rgb(217,234,211)">B ^ t</span>;
                      E = <span
                        style="background-color:rgb(207,226,243)">A ^ t</span><br>
                      >>> C, D, E<br>
                      <b>(0, 0, 0)</b><br>
                      >>> <b>A, B = 0, 1</b><br>
                      >>> t = A | B; C = A & B; D = B ^ t;
                      E = A ^ t<br>
                      >>> C, D, E<br>
                      <b>(0, 0, 1)</b><br>
                      >>> <b>A, B = 1, 0</b><br>
                      >>> t = A | B; C = A & B; D = B ^ t;
                      E = A ^ t<br>
                      >>> C, D, E<br>
                      <b>(0, 1, 0)</b><br>
                      >>> <b>A, B = 1, 1</b><br>
                      >>> t = A | B; C = A & B; D = B ^ t;
                      E = A ^ t<br>
                      >>> C, D, E<br>
                      <b>(1, 0, 0)</b></span><br>
                    <br>
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                  <div>Cheers,<br>
                  </div>
                  <div>Weston<br>
                  </div>
                  <br>
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                <div class="gmail_extra"><br>
                  <br>
                  <div class="gmail_quote">On Wed, Jan 15, 2014 at 8:42
                    PM, Mr. Clif <span dir="ltr"><<a
                        moz-do-not-send="true"
                        href="mailto:clif@eugeneweb.com" target="_blank">clif@eugeneweb.com</a>></span>
                    wrote:<br>
                    <blockquote class="gmail_quote" style="margin:0 0 0
                      .8ex;border-left:1px #ccc solid;padding-left:1ex">Sure


                      I can do it in three but two of the gates have to
                      have one inverting input each. Since gates often
                      come in quad packs it might be nice to find a
                      circuit that would use all four in a pack. Though
                      if it helps my fourth gate is just an inverter and
                      there are often left over ones from other
                      packages.<br>
                      <br>
                          Clif
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                        <div class="h5"><br>
                          <br>
                          <br>
                          <br>
                          <br>
                          On 01/15/2014 07:42 PM, Weston Turner wrote:<br>
                        </div>
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                        0 .8ex;border-left:1px #ccc
                        solid;padding-left:1ex">
                        <div>
                          <div class="h5"> I'm wondering if anyone can
                            implement this logic table with less than
                            four gates...<br>
                            <br>
                            A B | C D E<br>
                            -------------<br>
                            0 0 | 0 0 0<br>
                            0 1 | 0 0 1<br>
                            1 0 | 0 1 0<br>
                            1 1 | 1 0 0<br>
                            <br>
                            I figured out a way to implement it with
                            four gates but I'm wondering if it can be
                            reduced further...<br>
                            <br>
                            And if you can only figure out a way to do
                            it with four, then I'm curious to see if you
                            arrived at the same solution I did.<br>
                            <br>
                            Regards,<br>
                            Weston<br>
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